The present invention relates to a ferroelectric storage device.
A ferroelectric capacitor, though nonvolatile, has a characteristic capable of reading and writing data at a high speed. The ferroelectric capacitor is utilized for a ferroelectric memory (FeRAM (Ferroelectric Random Access Memory)) by making the use of this characteristic.
A readout characteristic of a cell potential of the ferroelectric memory, as in the case of a DRAM (Dynamic RAM), depends on a ratio of a ferroelectric capacitor that are provided in the cell to a bit line capacitor. With the high integration of the memory, as a memory area is reduced, a capacitor of the bit line decreases. As a result, in voltages applied to the ferroelectric capacitor and the bit line capacitor, the voltage applied to the ferroelectric capacitor decreases. With this decrease, an electric charge supplied to the bit line from the ferroelectric capacitor is reduced, and a readout margin of a sense amplifier decreases. A contrivance considered for this point is that the voltage applied to the ferroelectric capacitor of the cell is prevented from decreasing by adding a capacitor load onto the bit line.
In this case, however, a capacitor corresponding to the ferroelectric capacitor of the cell is needed as the capacitor added to the bit line. If such a capacitor is actualized by a gate capacitor, a source/drain capacitor or the ferroelectric capacitor, an increase in area is brought about. Further, the ferroelectric capacitor has a problem that restraint of a variation of the characteristic is insufficient, and so on. It should be noted that the following Patent documents 1 and 2 each disclose the ferroelectric capacitor.
[Patent document 1] Japanese Patent Laid-Open Publication No. 2001-319472
[Patent document 2] Japanese Patent Laid-Open Publication No. 2004-13951